The invention relates to a data processing circuit with a debug feature and a method of using such a circuit.
It is known to provide a data processor with a debug circuit that monitors data values that are output to memory. The debug circuit facilitates the analysis of the execution properties of programs at specific time points when specific conditions occur in the processor.
A known debug circuit causes an interruption of normal program execution when a data value equal to a specified value is output to memory. It is also known to specify a bit-mask in addition to the value, the interruption occurring when the data value is equal to the specified value at the bit positions that are enabled by the bit-mask.
It is also known to provide a data processor, such as a digital signal processor, with a vector processing capability. In this case, the data processor is able to process several arithmetic numbers in parallel in response to a vector instruction.
For example, a vector ADD instruction specifies two input operands. These operands are for example 64 bits long, the data processor handling these operands as containing four fields of 16 bit, each representing a 16 bit number. In response to the vector ADD instruction the data processor adds pairs of number from corresponding fields in the operands of the vector ADD instruction, without carry between different fields.
If applied to a vector processor the known debug circuit would make it possible to cause a debug interrupt when all fields of an operand have specified values, or when a mask-enabled field or combination of mask-enabled fields all have specified values.